The present invention relates to a counter used in semiconductor devices, and more specifically to a counter which can reduce propagation delay.
Counters used in semiconductor devices can be largely divided into two types. These are a counter employing a half adder structure and a ripple counter employing simple toggling. In the case of the ripple counter, the counter can be designed with a minimum area, but has increased propagation delay due to delays accumulated at every stage and may have an unstable value due to increased data skew.
Meanwhile, the counter employing the half adder structure has an increased area compared with the ripple counter, but has better characteristics in terms of data skew, since data output is synchronized with the clock of a flipflop. However, the counter employing the half adder structure has a carry propagation delay as a carry value can ripple across the half adder structure. This is a significant shortcoming of the counter employing the half adder structure.
To help alleviate this problem, a carry look ahead (CLA) structure was developed. The CLA structure is an adder of a type in which a carry can be quickly calculated if it will be generated or propagated through a 4-bit group. The CLA structure is used to reduce propagation time delay. This structure can reduce carry propagation delay, but has an output terminal whose output returns back to an input terminal. Accordingly, the CLA structure has disadvantage in rising/falling times of the output terminal.